The present invention relates to a device for testing memories which are used to store images, for instance.
In general, a semiconductor memory testing device has such an arrangement as shown in FIG. 1. An address signal is applied to a memory under test 200 from an address terminal 101 of a pattern generator 100, and data created by the pattern generator 100 at that time is provided from its data terminal 102 to the memory under test 200 and written therein at the specified address. Then, an address signal is applied from the pattern generator 100 to the memory under test 200 to read out therefrom the stored data. The thus readout data and data output from the pattern generator 100, that is, expected value data, are compared by a logical comparator 300 to determine whether the memory under test 200 is good or bad.
The pattern generator 100 is made up of an address generator 103, a data generator 104, a data memory 105, a clock control signal generator 106, and a sequence controller 107. The sequence controller 107 controls the address generator 103, the data generator 104, and the clock control signal generator 106. The address generator 103 generates an address signal which is applied to the memory under test 200. The data generator 104 generates, by a logical operation, data for input into the memory under test 200, that is, write data, and expected value data for input into the logical comparator 300. The data memory 105 also generates data for input into the memory under test 200 and expected value data for input into the logical comparator 300 which are prestored in the memory 105.
The data generator 104 is used to generate regular data and the data memory 105 to generate irregular, random data. A multiplexer 108 switches between the data generator 104 and the data memory 105. The clock control signal generator 106 generates a clock control signal which is applied to the memory under test 200.
The conventional semiconductor memory testing device shown in FIG. 1 cannot be employed for testing image memories recently developed.
Image memories heretofore employed have a random access port and a serial access port. The image memories are randomly accessed through the random access port. Through the serial access port an initial address is set and is then incremented one by one at high speed in response to a clock, for sequential access to respective memory addresses. A device for testing such dual port type memories has been proposed in Japanese Patent Kokai No. 269076/87, entitled "Semiconductor Memory Testing Device", laid open on Nov. 21, 1987.
Recently there has been developed an image memory which operates in pixel, plane, block and flash modes. In the case of providing a color display, a total of four bits for three pieces of color information R, G and B and one piece of control information C are employed as a smallest unit of pixel information PIX as shown in FIG. 2. Sometimes eight bits may be used for the pixel information PIX so as to increase the number of colors for display.
As shown in FIG. 2, each pixel information PIX at an arbitrary address is accessed using an address signal of N+1 bits A.sub.O to A.sub.N and individual pieces of pixel information PIX are sequentially stored in a memory in the direction of address depth. By sequentially or randomly reading out addresses in the direction of address depth, respective pieces of pixel information PIX can be read out and they can be written in a similar manner. This read/write mode is the pixel mode.
The plane mode is a mode of operation which accesses only single color information line by the same number of bits as that of the pixel information PIX. According to the plane mode, single color information can be re-written and read out in units of four bits, and a desired area of the display screen can be painted over with the color at high speed. The four-bit signal for effecting the re-write and the read-out at one time will hereinafter be referred to as plane information PLN.
The block mode is a mode of operation which reads and writes a memory space of, for example, a four-by-four bit plane, at one time. This mode is used for clearing, at high speed, a limited area of the display screen, for example, a multi-window.
The flash mode is a mode of operation in which data stored in a register built in the image memory is provided to all memory cells of one row address area whereby the same data can be written in the row address area at one time. For example, in the case of using a 16-bit address signal, one row address area is an area which includes 2.sup.8 address positions which are selected by all addresses whose high-order eight bits (a row address) have the same value, as shown in FIG. 3. On the other hand, respective address positions in each of row address areas M.sub.l to M.sub.k are selected by low-order eight bits (a column address) of the 16-bit address signal, where k=256. The image memory has a data register, and data stored in this data register is written into any one of the row address areas M.sub.l to M.sub.k at one time.
The image memory further has a mask register, in which mask data is stored. The mask data is used to mask desired bits of data during its write operation. Alternatively, new mask data obtained by ANDing the stored mask data and input mask data may also be used for masking desired bits.
Since the dual port type image memory has such various functions as mentioned above, it is difficult for the testing device to create expected value data for testing such functions.
In a test for determining whether data written in the flash mode can correctly be read out, it is particularly difficult to produce an expected value pattern under program control, because mask data must also be taken into account.